1. Field of the Invention
The present invention relates to an inverter control apparatus and an inverter control method which are useful for controlling, for example, PWM (Pulse Width Modulation) of a three-phase AC motor.
2. Description of the Related Art
FIG. 10 shows a controller of a common three-phase AC motor operating under PWM control. In the drawing, reference symbol B denotes a battery, and power is supplied from this battery B to a motor M by way of a contactor Z and an inverter circuit 100. For instance, the motor M is a three-phase induction motor mounted on a forklift. The contactor Z is formed from a contact point of a magnetic contactor. In the drawing, reference symbol C denotes a capacitor connected between power lines, and ST denotes a shunt for detecting an electric current flowing into the motor M. The shunt ST is formed from a resistor. Reference symbol PG denotes a pulse generator for detecting the revolutions per minute (RPM) of the motor M, and the pulse generator is formed from a known rotary encoder provided on a rotary shaft of the motor M.
The inverter circuit 100 is a circuit for driving the motor M by converting DC power of the battery B into AC power and corresponds to a known circuit constituted of six semiconductor switching elements; namely, an upper U-phase switching element Q1, a lower U-phase switching element Q2, an upper V-phase switching element Q3, a lower V-phase switching element Q4, an upper W-phase switching element Q5, and a lower W-phase switching element Q6. An element capable of operating at high speed; e.g., a MOS FET (field-effect transistor) or an IGBT (insulated gate bipolar transistor), is used as the semiconductor switching element. A diode is connected in parallel with each of the elements. A PWM signal output from a control section 101 is input to gates of the respective semiconductor switching elements Q1 to Q6. The respective semiconductor switching elements Q1 to Q6 are opened and closed during predetermined ON periods and predetermined OFF periods by this PWM signal. Consequently, an output from the inverter circuit 100 is taken out as a three-phase AC voltage, and a U-phase voltage, a V-phase voltage, and a W-phase voltage are supplied to the motor M.
The control section 101 has a CPU, memory, an A/D converter, a carrier signal generation circuit, and a PWM circuit. For example, a command value, such as a motor speed based on actuation of a lever of a forklift, a pulse output from the pulse generator PG, a current value detected by the shunt ST, or a voltage value of the battery B, is input to the control section 101. On the basis of the input values, the control section 101 generates a PWM signal required to control the motor M and outputs the signal to the inverter circuit 100. The motor controller using PWM control is described in, e.g., JP-A-2003-164190.
FIG. 11 is a view showing the configuration of a PWM signal generation section provided in the control section 101. Reference numeral 200 designates a carrier signal generation section for generating a carrier signal Ca; 207 designates a comparator for comparing the carrier signal Ca with the value of the U-phase command; 208 designates a comparator for comparing the carrier signal Ca with the value of a V-phase command; 209 designates a comparator for comparing the carrier signal Ca with the value of the W-phase command; and 210 designates a PWM circuit for generating a PWM signal on the basis of outputs from the comparators 207 to 209. Pulses imparted to the respective gates of the upper U-phase switching element Q1, the lower U-phase switching element Q2, the upper V-phase switching element Q3, the lower V-phase switching element Q4, the upper W-phase switching element Q5, and the lower W-phase switching element Q6 in the inverter circuit 100 shown in FIG. 10 are output as PWM signals from the PWM circuit 210.
FIG. 12 is a view for describing the principle for generating a PWM signal. As illustrated, the carrier signal Ca is a triangular wave having a given frequency, and the command values of respective phases are compared with the amplitude of the carrier signal Ca signal by the comparators 207 to 209. During a period in which the amplitude of the carrier signal Ca is greater than or equal to the command voltage, outputs from the comparators 207 to 209 become “H”. During a period in which the amplitude of the carrier signal Ca is less than the command voltage, outputs from the comparators 207 to 209 become “L”. Therefore, signals whose pulse widths vary in accordance with a change in the command voltage are obtained from the comparators 207 to 209. The signals are input to the PWM circuit 210, and the PWM circuit 210 generates six types of PWM signals, on the basis of the output from the comparators 207 to 209, for activating the upper and lower switching elements Q1 to Q6 of respective phases, such as those shown in FIG. 12. As can be seen from FIG. 12, during a period in which the amplitude of the carrier signal Ca is greater then or equal to the command voltages of respective phases, the upper switching elements of respective phases are activated, whilst the lower switching elements are deactivated. In contrast, during a period in which the amplitude of the carrier signal Ca is less than the command voltages, the lower switching elements of respective phases are activated, whereas the upper switching elements are deactivated.
Here, when the timing at which one of the pair of upper and lower switching elements of each phase is activated coincides with the timing at which the remaining element of is deactivated, a short circuit is formed from the upper and lower switching elements, whereupon a heavy current flows through the circuit, which may in turn destroy the element. For this reason, in reality, the PWM circuit 210 performs processing for producing a given time difference (dead time) between the activation timing of one of the pair of upper and lower switching elements and the deactivation timing of the other element.
However, in the case of such a method for generating a PWM signal through use of a single carrier signal Ca, when the motor voltage is in the neighborhood of 0 volt; that is, when a duty ratio between the pulses of PWM signals of respective phases is in the vicinity of 50:50, the periods of the dead times Td of respective phases overlap each other in the same position as shown in FIG. 13. During these periods, the inverter circuit 100 becomes inoperative, thereby raising a problem of a failure to output the motor voltage to be output.
As shown in FIG. 14, in order to solve this problem, the following method is proposed in JP-A-2002-27763 to be described later. Under this method, independent carrier signals are used for the respective phases, and command voltages of respective phases are compared with carrier signals of corresponding phases while the phases between the carrier signals are made different from each other by 120°, to thus obtain a PWM signal. In the proposed system, as shown in FIG. 16, carrier signal generation sections 201 to 203 are disposed respectively for the U-phase, V-phase, and W-phase to generate a U-phase carrier Cu, a V-phase carrier Cv, and a W-phase carrier Cw. As shown in FIG. 15, even when the pulse duty ratio between the PWM signals of respective phases is in the neighborhood of 50:50, the periods of the dead times Td of respective phases do not overlap each other in accordance with a difference between the phases of the carrier signals. Even when the motor voltage is in the neighborhood of 0 volt, the inverter circuit 100 operates to thus produce a predetermined voltage.